Placa de evaluación para FIFO AverLogic - AL460A-7-EVB-A0

AL460A HD-FIFO Evaluation Board, AverLogic

The AL460A HD-FIFO Module is designed for evaluating the AL460A HD-FIFO integrated chip. It has two embedded AL460A-7-PBF or AL460A-13-PBF chips operating in parallel, expanding the bus width to 32-bits. Control signals and data bus signals are available on two 50-pin connectors; one connector is reserved for write controls and the input data bus; the other one is for read controls and the output data bus.
The AL460 chip is designed with a straight forward bus interface, reducing implementation and debugging efforts, and helping customers develop faster and more efficiently. This board is especially designed and optimized to be easily integrated as an add-on module on existing systems, significantly reducing interface engineering issues commonly found in retrofit efforts.

Memoria FIFO 8M x 32 bits, densidad de 256 Mbits
Operaciones de escritura / lectura síncrona de 32 bits de 150 MHz (AL460A-13-EVB-A0), 75 MHz (AL460A-7-EVB-A0) máximo
Rendimiento de 4,8 Gbps máximo
Fuente de alimentación de 3,3 V
Control de E/S programable
Admite modo de búfer doble (acceso a bastidores superiores e inferiores 4M x 32 bits)
Control de polaridad seleccionable